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Intel commented on the delay of 10-nm standards and told about the future 14-nm products

Ever since Intel announced that the massive output of its 10-nm chips was postponed until 2019, there were questions about what caused the delay and how the fourth generation of 14-nm architecture could hold a blow. At the 46th Annual JP Morgan Technology Conference Dr. Venkata “Murty” Renduchintala (Venkata “Murthy” Renduchintala), responsible for the development of processor architectures in Intel, touched on these topics in some detail.



When asked about the future of Intel’s 14-nm process (we are talking about 14-nm +++, if Intel continues to use this nomenclature), Mr. Renduchintala said: “We have discovered huge optimization opportunities within our 14-nanometer process. In fact, from the very first generation of our 14-nm standards to the latest version of the 14-nm solution, we were able to improve performance by 70% as a result of these modifications and important changes. And this, frankly, gives us time to achieve high yields of 10-nm crystals before transferring to this new technical process of the main products. Therefore, we are satisfied with the plans to develop 14-nm products that will provide us with leading positions in the next 12-18 months, while we continue to optimize the cost structure and profitability of our 10-nm portfolio. “

This is partly true. 14-nm + technical process Intel used slightly higher FinFET-transistors and allowed to place elements denser on the substrate. This enabled Kaby Lake to reach higher frequencies and improve power consumption compared to Skylake. Similarly, 14-nm ++ norms allowed Intel to release quad-core processors (4C / 4T) with the same TDP values, which previously corresponded to dual-core four-stream (2C / 4T) solutions. But while a 70 percent improvement in performance reflects reality, there are limits to everything. Let Intel update some mobile processors Core i3 from 2C / 4T to 4C / 4T, but it is unlikely that the company will present a Core i3 or i5 6C / 6T chip with a TDP of 15 W based on even the most advanced 14-nm +++ architecture.

The situation with Intel’s 14-nm standard is similar to what GlobalFoundries and TSMC did with their own technological processes: just Intel does not call them completely new standards. But there is an inevitable limit to optimizations, and given that Intel has never planned to use a 14-nm rate for so long, now it seems the company has already made the most improvements that you can count on.

When Venkata Renduchintala was asked about plans for 10 nm, he said: “We supply 10-nanometer solutions in small volumes. I think that if you recall what we originally planned to implement within the 10-nanometer process technology in early 2014, you’ll see that the goals were set very aggressive. We aimed at a 2.7-fold scaling factor compared to 14-nm, which was then only deployed. And at the same time, within the 14-nanometer technology process, we realized 2.4-fold scaling in comparison with 22-nm standards, therefore the goals of our engineering team in terms of scaling transistors were extremely ambitious … “

By the way, Intel claims that its 14-nm standard differs by a higher (by 1.23 times) density of transistors compared to “other” technical processes (however, it is not clear whether the comparison is with Samsung or TSMC). The technologist noted that such high goals were imposed on additional technical difficulties caused by the transition to EUV-nanolithography while preserving the four photomasks.

All these words serve as an explanation of the problems with the delay in the transition of Intel to 10-nm norm: the company just swung to the target, which it was too tough for. Technological standards of Intel have always been ahead of TSMC, Samsung or GlobalFoundries: Intel’s 14-nm chips are roughly equivalent to the 10-nm process technology of these companies. With 10-nm standards, Intel wanted to go ahead again for the time it was spent to master them (this was before the announcement of a new delay, as early as 2019).

While the other semi-conductor forges for BEOL (back end of line) use two photomasks (SADP, self-aligned double patterning), Intel uses four (SAQP). This not only increases the cost of production, but also complicates the process and slows down printing. It is not clear why Intel decided to continue to adhere to the SAQP for the BEOL in 10-nm standards, but Mr. Renduchintal’s comments are quite eloquent: the share of the yield of 10-nm crystals is low, and the cost of printing is too high. The company releases 10-nm processors in extremely limited volumes, but sees no reason to implement a large-scale transition to new standards, while 14-nm is good for it.

Will AMD be able to take advantage of this situation? Perhaps, provided that she manages to switch to 7-nm standards in chips Ryzen 2 with GlobalFoundries. But it’s worth remembering that Intel is paying less attention to the PC market, focusing on data centers. Corporate users are much more inert, and therefore AMD Epyc chips have not achieved much success (no one even inside AMD counts that these processors will occupy more than 4-6% of the server market this year).

This is Intel’s first such serious technological delay in the last two decades. The company can not afford to rest on its laurels and ignore rivals, but still the delay of 10-nm standards until 2019 will not be a disaster.

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